Nikita Nikitin homepage

Nikita Nikitin

Research Associate
Department of Software
Technical University of Catalonia

Campus Nord, Edifici Omega, S108
Jordi Girona Salgado 1-3
08034 Barcelona
Spain

Phone: +34-93-4137861
E-mail: nnikitin at lsi dot upc dot edu
nikita i nikitin at gmail dot com


Curriculum Vitae: pdf

Research Interests

	Architecture of Chip Multiprocessors and many-core Systems-on-Chip Electronic Design Automation (EDA) algorithms for VLSI circuits Synthesis and optimization of on-chip interconnection networks (NoCs)

Research and Industrial Experience

	My background comes from Electronic Design Automation (EDA) for VLSI circuits. During the university studies and long-term internship with Intel Corporation, I participated in several research and industrial projects aimed at various stages of the EDA flow: from Static Timing Analysis, Technology Mapping and Gate Sizing to Pre-silicon Co-simulation and Layout Compaction. Ph.D. research opened a new page of my experience: the architectures of many-core on-chip systems. I started working on the models and tools for synthesis and optimization of Networks-on-Chip and application-specific Systems-on-Chip. The issues included analytical performance models, physical aspects of link allocation and routing, and task assignment for many-core systems. The latest research project is dedicated to architectural design space exploration for hundred- and thousand-core Chip Multiprocessors. This research combines the issues of Computer Architecture and Design Automation for power/performance/area optimization. (Summary)



Incofab Code Release

	Incofab is a C++ framework for architectural exploration of hierarchical chip multi-processors (CMPs). Given a description of the architectural design space in terms of the models for CMP components (e.g. core architectures, cache sizes, interconnect topologies, etc.) and constraints (e.g. area and power) the tool searches for the architectures that maximize the system throughput in instructions-per-cycle, IPC. A quick starter manual and pointers to the theoretical background are included into the current release. The tool is distributed under the Apache 2.0 license. Version 0.2. May 10, 2013. Download Version 0.1. Dec 11, 2012. Download



Publications

	J. de San Pedro, N. Nikitin, J. Cortadella, J. Petit. "Physical planning for the architectural exploration of large-scale chip multiprocessors." In Proc. The 7th International Symposium on Networks-on-Chip (NOCS), April 2013. J. Cortadella, J. de San Pedro, N. Nikitin, J. Petit. "Physical-aware system-level design for tiled hierarchical chip multiprocessors." In Proc. International Symposium on Physical Design (ISPD), March 2013. N. Nikitin and J. Cortadella. "Analytical models for architectural exploration of many-core chip multiprocessors." In Proc. Barcelona Forum on Ph.D. Research in Information and Communication Technologies, October 2012. N. Nikitin, J. de San Pedro, J. Carmona and J. Cortadella. "Analytical performance modeling of hierarchical interconnect fabrics." In Proc. The 6th International Symposium on Networks-on-Chip (NOCS), May 2012. N. Nikitin and J. Cortadella. "Static task mapping for tiled chip multiprocessors with multiple voltage islands." In Proc. Architecture of Computing Systems (ARCS), March 2012. *Nominated for Best Paper Award.* N. Nikitin, S. Chatterjee, J. Cortadella, M. Kishinevsky and U. Ogras. "Physical-aware link allocation and route assignment for chip multiprocessing." In Proc. The 4th International Symposium on Networks-on-Chip (NOCS), May 2010. N. Nikitin and J. Cortadella. "A performance analytical model for Network-on-Chip with constant service time routers." In Proc. International Conf. Computer-Aided Design (ICCAD), November 2009.



Degrees and Theses

	Ph.D. in Computer Engineering, April 2013 Technical University of Catalonia (UPC) Thesis: “Automatic synthesis and optimization of Chip Multiprocessors.” Download Advisor: Prof. Jordi Cortadella M.S. in Computer Science, June 2007 Moscow Institute of Physics and Technology (MIPT) Thesis: “Study of the gate sizing algorithms for VLSI circuit optimization.” B.S. in Computer Science, June 2005 Moscow Institute of Physics and Technology (MIPT) Thesis: “Implementation and study of the Voronoi core construction algorithms for VLSI layouts.”