Ph.D. thesis advisor
-
[VO20]
-
Alex Vidal-Obiols.
Algorithmic Techniques for Physical Design: Macro Placement and
Under-the-Cell Routing.
PhD thesis, Universitat Politècnica de Catalunya, January 2020.
Co-advised with Jordi Petit.
[ bib |
]
-
[Mor19]
-
Alberto Moreno.
Synthesis of Variability-Tolerant Circuits with Adaptive
Clocking.
PhD thesis, Universitat Politècnica de Catalunya, March 2019.
[ bib |
]
-
[Mac19]
-
Lucas Machado.
Logic Decomposition and Adaptive Clocking for the Optimization
of Digital Circuits.
PhD thesis, Universitat Politècnica de Catalunya, February 2019.
[ bib |
]
-
[dSP17]
-
Javier de San Pedro.
Structure discovery techniques for circuit design and process
model visualization.
PhD thesis, Universitat Politècnica de Catalunya, October 2017.
[ bib |
]
-
[Jai17]
-
Palkesh Jain.
Algorithms and Methodologies for Interconnect Reliability
Analysis of Integrated Circuits.
PhD thesis, Universitat Politècnica de Catalunya, May 2017.
Co-advised with Sachin S. Sapatnekar.
[ bib |
]
-
[Nik13]
-
Nikita Nikitin.
Automatic Synthesis and Optimization of Chip Multiprocessors.
PhD thesis, Universitat Politècnica de Catalunya, April 2013.
[ bib |
]
-
[GO11]
-
Marc Galceran-Oms.
Automatic Pipelining of Elastic Systems.
PhD thesis, Universitat Politècnica de Catalunya, September 2011.
Co-advised with Mike Kishinevsky.
[ bib |
]
-
[Buf10]
-
Dmitry Bufistov.
Performance Optimization of Elastic Systems.
PhD thesis, Universitat Politècnica de Catalunya, December 2010.
[ bib |
]
-
[Gor10]
-
Kyller Costa Gorgônio.
Towards the Automatic Synthesis of Asynchronous Communication
Mechanisms.
PhD thesis, Universitat Politècnica de Catalunya, December 2010.
[ bib |
]
-
[Bañ08]
-
David Bañeres.
Logic Synthesis Techniques for High-Speed Circuits.
PhD thesis, Universitat Politècnica de Catalunya, February 2008.
Co-advised with Mike Kishinevsky.
[ bib |
]
-
[Cla05]
-
Robert Clarisó.
Abstract Interpretation Techniques for the Verification of
Timed Systems.
PhD thesis, Universitat Politècnica de Catalunya, September 2005.
[ bib |
]
-
[Car04]
-
Josep Carmona.
Structural Methods for the Synthesis of Well-Formed Concurrent
Specifications.
PhD thesis, Universitat Politècnica de Catalunya, March 2004.
[ bib |
]
-
[Peñ03]
-
Marco A. Peña.
Relative Timing Based Verification of Concurrent Systems.
PhD thesis, Universitat Politècnica de Catalunya, April 2003.
Co-advised with Enric Pastor.
[ bib |
]
-
[Cor01]
-
Gianluca Cornetta.
Design and Analysis of Variable-Delay Arithmetic Units.
PhD thesis, Universitat Politècnica de Catalunya, December 2001.
[ bib ]
-
[Roi97]
-
Oriol Roig.
Formal Verification and Testing of Asynchronous Circuits.
PhD thesis, Universitat Politècnica de Catalunya, May 1997.
[ bib |
]
-
[Mus96]
-
Enric Musoll.
High-level and logic synthesis techniques for low power.
PhD thesis, Universitat Politècnica de Catalunya, July 1996.
[ bib |
]
-
[Pas96]
-
Enric Pastor.
Structural Methods for the Synthesis of Asynchronous Circuits
from Signal Transition Graphs.
PhD thesis, Universitat Politècnica de Catalunya, April 1996.
[ bib |
]
-
[S9́6]
-
Fermín Sánchez.
Loop pipelining with resource and timing constraints.
PhD thesis, Universitat Politècnica de Catalunya, January 1996.
[ bib |
]
-
[Bad94]
-
Rosa M. Badia.
High-level synthesis of asynchronous circuits.
PhD thesis, Universitat Politècnica de Catalunya, July 1994.
[ bib ]
-
[Jov89]
-
Teodor Jové.
Design of instruction memories for pipelined processors.
PhD thesis, Universitat Politècnica de Catalunya, October 1989.
[ bib ]
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