`ifndef __REGISTERS__
`define __REGISTERS__

// A simple rising-edge triggered register.
// The parameter N indicates the number of bits.

module register (D, Q, clk);
  parameter N=1;
  input [N-1:0] D;
  output reg [N-1:0] Q;
  input clk;
  always @(posedge clk) Q <= D;
endmodule

// A rising-edge triggered register with synchronous reset.
// The parameter N indicates the number of bits.
// The parameter INIT_VALUE is the initial value
// acquired by the register after reset.

module register_rst (D, Q, clk, rst);
  parameter N=1;
  parameter INIT_VALUE=0;
  input [N-1:0] D;
  output reg [N-1:0] Q;
  input clk, rst;

  always @(posedge clk)
    if (rst) Q <= INIT_VALUE;
    else Q <= D;
endmodule

// A rising-edge triggered register with enable.
// The parameter N indicates the number of bits.
// The value of the register changes only when the
// enable signal is asserted.

module register_en (D, Q, clk, en);
  parameter N=1;
  input [N-1:0] D;
  output reg [N-1:0] Q;
  input clk, en;

  always @(posedge clk)
    if (en) Q <= D;
endmodule

// A rising-edge triggered register with synchronous reset and enable.
// The parameter N indicates the number of bits.
// The parameter INIT_VALUE is the initial value
// acquired by the register after reset.
// The value of the register changes only when the
// enable signal is asserted.

module register_rst_en (D, Q, clk, en, rst);
  parameter N=1;
  parameter INIT_VALUE=0;
  input [N-1:0] D;
  output reg [N-1:0] Q;
  input clk, en, rst;

  always @(posedge clk) begin
    if (rst) Q <= INIT_VALUE;
    else if (en) Q <= D;
  end
endmodule

`endif